Changelog
All notable changes to this project will be documented in this file.
The format is based on Keep a Changelog, and this project adheres to Semantic Versioning.
Unreleased
v0.1.1 - 2024-03-05
Added
Changed
The MulticycleDiv implementation has been simplified in two ways:
The internal divider and signed/unsigned conversion is now controlled by an FSM instead of streaming signed/unsigned units.
The internal divider uses a restoring algorithm by default.
Net effect is that a 32-bit MulticycleDiv requires 12% fewer storage elements and 37% fewer LUTs.
Fixed
The internal NonRestoringDiv now requires one extra cycle of latency to latch inputs, so that inputs need not be held while a divide is in progress.
This also has the side effect of reducing LUT usage at the cost of extra registers.
v0.1.0 - 2024-02-29
Initial release.
Added
Add multicycle multipier core, pipelined multiplier, and multicycle long and non-restoring dividers.
32 and 64-bit dividers created with this library are compliant w/ RISC-V specification for division-by-zero, signed overflow, and remainder sign.