Changelog

All notable changes to this project will be documented in this file.

The format is based on Keep a Changelog, and this project adheres to Semantic Versioning.

Unreleased

[v0.2.0] - 2024-06-26

v0.2.0 does not introduce any new functionality, and is a maintenance release. The minimum Amaranth version is now v0.5.0 to take advantage of its streams implementation.

Added

Changed

  • Use Amaranth v0.5.0 from PyPI as minimal version.

  • Convert modules to use Amaranth streams instead of custom Signatures.

    • Nominally compatible with smolarith v0.1.x, but the Amaranth version bump warrants a minor release bump.

  • Simulation tests now use async functions and testbench semantics (signal updates occur immediately, not at the the next clock edge).

  • Refactor tests:

    • Take advantage of the combination of fixture parameterization direct test parameterization to clean up tests and reduce test code duplication.

    • Flatten test directory structure.

    • Improve (mul) and add (div) random value testbenches.

  • Use PDM to install RTD dependencies.

  • Quality-of-life changes for DoIt tasks. Tasks are meant mostly for my internal use.

  • Use dynamic version based on git tags. Because I keep forgetting to update it manually :).

Fixed

  • Correct license type (was MIT, BSD 2-Clause intended).

v0.1.1 - 2024-03-05

Added

  • Add restoring divider internal implementation.

  • Add DoIt tasks for benchmarking and Verilog generation. These are meant mostly for development.

Changed

  • The MulticycleDiv implementation has been simplified in two ways:

    • The internal divider and signed/unsigned conversion is now controlled by an FSM instead of streaming signed/unsigned units.

    • The internal divider uses a restoring algorithm by default.

    Net effect is that a 32-bit MulticycleDiv requires 12% fewer storage elements and 37% fewer LUTs.

Fixed

  • The internal NonRestoringDiv now requires one extra cycle of latency to latch inputs, so that inputs need not be held while a divide is in progress.

    This also has the side effect of reducing LUT usage at the cost of extra registers.

v0.1.0 - 2024-02-29

Initial release.

Added

  • Add multicycle multipier core, pipelined multiplier, and multicycle long and non-restoring dividers.

    32 and 64-bit dividers created with this library are compliant w/ RISC-V specification for division-by-zero, signed overflow, and remainder sign.